1. Field of the Invention
The present invention is related to memory devices, and more specifically to a gated-feedback sense amplifier circuit for sensing voltages of single-ended local bit-lines to generate a global bit-line output.
2. Description of Related Art
Sense amplifiers are used within dynamic logic circuits and more particularly within memory circuits to detect signals provided by local bit-line outputs of the storage array to generate a global bit-line output signal. The read access delay of the memory is generally limited by the capacitance of the bit-lines and the speed at which the voltage present on a bit-line can be reliably detected.
The sense amplifiers typically employed in memory devices are designed to quickly resolve the logic state from the voltage present on the local bit-line. The typical sense amplifier for single-ended bit-line sensing, such as in (embedded dynamic random-access memory) eDRAM designs is formed by a pair of cross-coupled inverters and an input circuit that buffers the local bit-line voltage(s). While differential bit-lines can be sensed directly due to their symmetrical inputs affecting the inputs to the sense amplifier symmetrically, with a single-ended bit-line input, the sense amplifier input is buffered since the sense amplifier's input also sources current due to the cross-coupled inverter configuration. The buffering causes additional delay, making a single-ended design typically slower than a differential design, which affects the read timing margin of the device.
It would therefore be desirable to provide a memory read circuit for a single-ended bit-line memory that has reduced delay/improved timing margin, along with reduced area and power consumption.